1. Field of the Invention
The present invention relates to a semiconductor device including a non-volatile memory cell, and to a method of manufacturing the same.
2. Description of the Related Art
FIG. 29 shows the cross-sectional structure of a plurality of conventional non-volatile memory cells in a channel width direction (i.e., direction perpendicular to channel current flowing direction) (see IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 5, MAY 2002, p 264-266). In FIG. 29, reference numerals 81, 82, 83, 84, 85 and 86 denote silicon substrate, isolation film, tunnel insulating film, floating gate electrode, interelectrode insulating film and control gate electrode, respectively.
As seen from FIG. 29, most of two adjacent floating gate electrodes in the channel width direction (about 50% in the example shown in FIG. 29) face via the isolation film 82.
The scale-down of memory cell further advances, and thereby, a distance L1 between floating gate electrodes 84 becomes shorter. The shorter the distance L1 becomes, the larger the capacitance between adjacent floating gate electrodes (parasitic capacitance between floating gate electrodes) becomes.
As a result, since the scale-down of memory cell is now advancing, the parasitic capacitance between floating gate electrodes must be considered as well as the parasitic capacitance between the floating gate electrode 84 and the silicon substrate 81.
An increase of the parasitic capacitance between floating gate electrodes causes a cell interference. According to the cell interference, write/erase state of adjacent memory cells gives influence to memory cell operation characteristic. The cell interference is a factor of causing memory malfunction.
The following is a description on another problem in conventional non-volatile memory cells.
FIG. 30 shows the cross-sectional structure of a plurality of conventional non-volatile memory cells in a channel length direction (channel current flowing direction) (see JPN. PAT. APPLN. KOKAI Publication No. 2002-203919). In FIG. 30, reference numerals 87 and 88 denote source/drain region and interlayer insulating film, respectively. In FIG. 30, the same reference numerals as FIG. 29 are used to designate portions corresponding to FIG. 29.
As seen from FIG. 30, two adjacent floating gate electrodes 84 in the channel length direction entirely face each other via the interlayer insulating film 88.
The scale-down of memory cell further advances, and thereby, a distance L2 between floating gate electrodes 84 becomes shorter. The shorter the distance L2 becomes, the larger parasitic capacitance C1 between upper surfaces of adjacent floating gate electrodes 84 shown in FIG. 31A becomes.
As a result, since the scale-down of memory cell is now advancing, the parasitic capacitance C1 must be considered in addition to parasitic capacitance C2 between sidewalls of adjacent floating gate electrodes 84 (see FIG. 31B). In particular, the parasitic capacitance C1 remarkably increases if high dielectric constant films such as alumina film or tantalum oxide film are used as the interelectrode insulating film 85.
The increase of the parasitic capacitance C1 causes cell interference. The cell interference is a factor of causing memory malfunction.